This invention relates generally to methods and circuit configurations for measuring signal propagation delays, and in particular for measuring signal propagation delays through data paths of integrated circuits.
Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that guarantee superior speed performance. This leads IC manufactures to carefully test the speed performance of their designs.
FIG. 1 depicts a conventional test configuration 100 for determining the signal propagation delay of a test circuit 110 in a conventional IC 115. A tester 120 includes an output lead 125 connected to an input pin 130 of IC 115. Tester 120 also includes an input line 135 connected to an output pin 140 of IC 115.
Tester 120 applies an input signal to input pin 130 and measures how long the signal takes to propagate through test circuit 110 from input pin 130 to output pin 140. The resulting time period is the timing parameter for test circuit 110, the path of interest. Such parameters are typically published in literature associated with particular ICs and/or used to model the speed performance of circuit designs that employ the path of interest.
Conventional test procedures are problematic for at least two reasons. First, many signal paths within a given IC are not directly accessible via input and output pins, and therefore cannot be measured directly. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the path of interest is short. For example, if a tester accurate to one nanosecond measures a propagation delay of one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to assume the timing parameter was two nanoseconds, the worst-case scenario. If ICs are not assigned worst-case values, some designs will fail. Thus, IC manufacturers tend to add relatively large margins of error, or xe2x80x9cguard bands,xe2x80x9d to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to guarantee their full speed performance, which could cost them customers in an industry where speed performance is paramount.
Programmable logic devices (PLDS) are well-known digital integrated circuits that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic is configured by loading configuration data into internal configuration memory cells that define how the CLBs, interconnections, and IOBs are configured.
Each programming point, CLB, interconnection line, and IOB introduces some delay into a signal path. The many potential combinations of delay-inducing elements make timing predictions particularly difficult. FPGA designers use xe2x80x9cspeed filesxe2x80x9d that include resistance and capacitance values for the various delay-inducing elements and combine them to establish delays for desired signal paths. These delays are then used to predict circuit timing for selected circuit designs implemented as FPGA configurations. FPGA timing parameters are assigned worst-case values to ensure FPGA designs work as indicated.
Manufacturers of ICs, including FPGAs, would like to guarantee the highest speed performance possible without causing ICs to fail to meet the guaranteed timing specifications. More accurate measurements of circuit timing allow IC designers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate means of characterizing IC speed performance.
The present invention addresses the need for an accurate means of characterizing IC speed performance. The inventive circuit is particularly useful for testing programmable logic devices, which can be programmed to include both the signal path of interest and a majority of the requisite test circuitry.
In accordance with the invention, a test circuit (e.g., a signal path selected for analysis) is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions, or edges, on the test-circuit input node. To establish the average period of the oscillator, these signal transitions are counted over a predetermined time period, or the time period for a predetermined large count is measured. This average period is then related to the average signal propagation delay through the test circuit.
Signal paths often exhibit different propagation delays for falling and rising edges, due to imbalanced driver circuits, for example. The trouble with providing average propagation delays is that the worst-case delay is generally greater than the average delay. Consider, for example, the case where a signal path delays falling edges by 2 nanoseconds and rising edges by 3 nanoseconds. The average, 2.5 nanoseconds, is shorter than the worst-case delay associated with rising edges. Unfortunately, the average delay does not indicate whether the delays associated with falling and rising edges are different. Thus, a conservative guard band must be added to the average delay.
The present invention reduces the requisite guard band by separately measuring the signal propagation delays associated with rising and falling edges traversing the test circuit. The oscillator includes a phase detector with an output node connected to a pulse generator, or one-shot. The phase detector also has an in put node connected to the output node of the pulse generator through the test circuit so that the phase detector, pulse generator, and test circuit form a closed loop.
The pulse generator sends test pulses through the test-circuit to the phase detector. The phase detector responds to either the high-to-low or low-to-high signal transitions of each test pulse from the test circuit by causing the pulse generator to generate the subsequent test pulse; the phase detector ignores the other type of signal transition. The loop oscillates at a frequency that is determined by the signal propagation delay associated with only one type of signal transition because the phase discriminator initiates pulses in response to only one type of signal transition. The signal propagation delay for the selected type of signal transition can then be calculated from the oscillation frequency.
In one embodiment the phase discriminator includes selective inverters that enable the closed loop to oscillate at a frequency determined by the signal propagation time for either rising or falling edges propagating through the test circuit. The worst-case delay associated with the test circuit is simply the longer of the-two delays. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.